A microprocessor typically includes a memory management subsystem that provides segmentation and paging. For example, the well known Intel X86.TM. /Pentium.TM. microprocessors include a memory management subsystem that provides a segment translator and a page translator.
Address generation in a microprocessor that implements segmentation and paging typically requires adding a constant or a displacement, a (logical) base, and a segment base to generate an address. For example, a typical address generation unit 100 is shown in prior art FIG. 1. Address generation unit 100 uses a 2-to-1 multiplexer to select either a constant or a displacement and then adds the multiplexer output, a (logical) base, and a segment base to generate a 32-bit address. In particular, prior art address generation unit 100 generates the lower 16 bits (bits [15:0]) of the 32-bit address by selecting either a constant or a displacement in a 16-bit multiplexer 110, adding the output value of multiplexer 110 to the lower 16 bits of the (logical) base in a 16-bit carry-propagate adder 102, and then adding the output value of 16-bit carry-propagate adder 102 and a lower 16 bits of the segment base using a 16-bit carry-propagate adder 104. Prior art address generation unit 100 generates the upper 16 bits (bits [31:16]) of the 32-bit address by selecting either a constant or a displacement in a 16-bit multiplexer 112, adding the output value of multiplexer 112 to the upper 16 bits of the base using a 16-bit carry-propagate adder 106, which receives a carry-in value from a carry-out value of 16-bit carry-propagate adder 102, clearing the output value of 16-bit carry-propagate adder 106 using 16-bit AND-gate 114, and then adding the output of 16-bit AND-gate 114 and an upper 16 bits of the segment base using a 16-bit carry-propagate adder 108, which receives a carry-in value from a carry-out value of 16-bit carry-propagate adder 104. The clearing or zeroing of the 16-bit carry-propagate adder 106 is used during 16-bit mode, in which only the lower 16 bits of the constant or displacement and the (logical) base affect the 32-bit address output. In 32-bit mode, the 16-bit AND-gate 114 output is equal to the 16-bit carry-propagate adder 106 output allowing all 32 bits of the constant or displacement and the (logical) base to affect the 32-bit address output. Accordingly, prior art address generation unit 100 generates the 32-bit address using 16-bit carry-propagate adders 102, 104, 106, and 108.